Tutorial Week 10
Describe a two-level page table and how it is used to translate a virtual address into a physical address.
Given a two-level page table (in physical memory), what is the average number of physical memory accesses per virtual memory access in the case where the TLB has a 100% miss ratio, and the case of a 95% hit ratio
What are the two broad categories of events causing page faults? What other event might cause page faults?
Translate the following virtual addresses to Physical Addresses using the TLB. The system is a R3000. Indicate if the page is mapped, and if so if its read-only or read/write.
The EntryHi register currently contains 0x00000200.
The virtual addresses are 0x00028123, 0x0008a7eb, 0x0005cfff,0x0001c642, 0x0005b888, 0x00034000.
TLB EntryHi EntryLo 0x00028200 0x0063f400 0x00034200 0x001fc600 0x0005b200 0x002af200 0x0008a100 0x00145600 0x0005c100 0x006a8700 0x0001c200 0x00a97600
Describe an inverted page table and how it is used to translate a virtual address into a physical address.
Describe a hashed page table and how it is used to translate a virtual address into a physical address.
Of the three page table types covered in lectures, which ones are most appropriate for large virtual address spaces that are sparsely populated (e.g. many single pages scattered through memory)?
What is temporal and spatial locality?