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School of Computer Science & Engineering
University of New South Wales
 Advanced Operating Systems 
 COMP9242 2002/S2 

Address Space Usage vs. TLB Coverage

• Each TLB entry maps one virtual page.
• On TLB miss, reloaded from page table (PT), which is in memory.
• Some TLB entries need to map page table.
  • E.g. 32-bit page table entries, 4kb pages.
  • One PT page maps 4Mb.
• Traditional UNIX process has 2 regions of allocated virtual address space:
  • low end: text, data, heap,
  • high end: stack.
  ==> 2-3 PT pages are sufficient to map most address spaces.

Sparse address space use ties up PT entries

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