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School of Computer Science & Engineering
University of New South Wales
 Advanced Operating Systems 
 COMP9242 2002/S2 

TLB Issues

Associativity

• First TLB (VAX-11/780,[CE85]) was 2-way associative.
• Most modern architectures have fully associative TLBs.
• Exceptions:
  • i486 (4-way),
  • Pentium, Pentium-6 (4-way),
  • IBM RS/6000 (2-way).
• Superpages ==> fully associative TLB

Size (I-TLB + D-TLB)

Architecture	TLB Size
VAX	64-256
ix86	32-32+64
MIPS	96-128
SPARC	64
Alpha	32-128+128
RS/6000	32+128
PA-8000	96+96
Itanium	64+96

Note: not much growth in 20 years!

TLB coverage

• Memory sizes are increasing.
• Number of TLB entries are more-or-less constant.
• Page sizes are growing very slowly.
• Total amount of RAM mapped by TLB is not changing much.
• Fraction of RAM mapped by TLB is shrinking dramatically.
• Modern architectures have very low TLB coverage.
• Also, many modern architectures have software-loaded TLBs.
• General increase in TLB miss handling cost.

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