[UNSW] COMP3231/9201/3891/9283 Operating Systems 2007/s1

Assignment 3: Virtual Memory

Due Date: 8am (08:00), Monday 4th June (Week 14)

Worth 30 marks (of the 100 available for the class mark component of the course)

The 10% bonus for one week early applies

The extra 5% bonus for a submitted, working assignment within 48 hours of release, also applies

See course intro for exact details. The notional release time is midnight, Monday, 14th May

Up to a 20% bonus is available for the advanced part of the assignment

To attempt the advanced part, you must finish the standard assignment at least one week early, and get permission from Kevin.

Any bonus awarded for the advanced part can be used to make up for lost marks in any class mark component of the course. The familiarisation questions contained herein are the subject of your week 12 tutorial. Please answer the questions and bring them to your tutorial.

Contents

Introduction

In this assignment you will implement the virtual memory sub-system of OS/161. The existing VM implementation in OS/161, dumbvm, is a minimal implementation with a number of shortcomings. In this assignment you will adapt OS/161 to take full advantage of the simulated hardware by implementing management of the MIPS software-managed Translation Lookaside Buffer (TLB). You will write the code to manage this TLB. You will also write code to manage system memory.

If you attempt the advanced portion of this assignment, you will implement paging, the mechanism by which memory pages of an active process can be sent to disk when memory is needed, and restored to memory when required by the program.

The System/161 TLB

In the System/161 machine, each TLB entry includes a 20-bit virtual page number and a 20-bit physical page number as well as the following five fields:
  • global: 1 bit; if set, ignore the PID bits in the TLB.
  • valid: 1 bit; set if the TLB entry contains a valid translation.
  • dirty: 1 bit; enables writing to the page referenced by the entry; if this bit is 0, the page is only accessible for reading.
  • nocache: 1 bit; unused in System/161. In a real processor, indicates that the hardware cache will be disabled when accessing this page.
  • pid: 6 bits; a context or address space ID that can be used to allow entries to remain in the TLB after a context switch.
All these bits/values are maintained by the operating system. When the valid bit is set, the TLB entry contains a valid translation. This implies that the virtual page is present in physical memory. A TLB miss occurs when no TLB entry can be found with a matching virtual page and address space ID (unless the global bit is set in which case the address space ID is ignored) and a valid bit that is set.

For this assignment, you may ignore the pid field. Note, however, that you must then flush the TLB on a context switch (why?).

The System/161 Virtual Address Space Map

The MIPS divides its address space into several regions that have hardwired properties. These are:
  • kseg2, TLB-mapped cacheable kernel space
  • kseg1, direct-mapped uncached kernel space
  • kseg0, direct-mapped cached kernel space
  • kuseg, TLB-mapped cacheable user space
Both direct-mapped segments map to the first 512 megabytes of the physical address space.

The top of kuseg is 0x80000000. The top of kseg0 is 0xa0000000, and the top of kseg1 is 0xc0000000.

The memory map thus looks like this:

Address Segment Special properties
0xffffffff kseg2  
0xc0000000  
0xbfffffff kseg1  
0xbfc00180 Exception address if BEV set.
0xbfc00100 UTLB exception address if BEV set.
0xbfc00000 Execution begins here after processor reset.
0xa0000000  
0x9fffffff kseg0  
0x80000080 Exception address if BEV not set.
0x80000000 UTLB exception address if BEV not set.
0x7fffffff kuseg  
0x00000000  

Setting Up Assignment 3

Remember to use a 3231 subshell (or continue using your modified PATH) for this assignment, as outlined in ASST0. In this section, you will (again) be setting up the darcs repository that will contain your code. Only one of you needs to do the following. We suggest your partner sit in on this part of the assignment.

Advanced Assignment

Students who wish to attempt the advanced part of this assignment may gain up to an extra 6 marks (20%) for one (or multiple) of the following:
  • (easy) Shared pages and copy-on-write.
  • (hard) Implement mmap() and related system calls.
  • (hard) Implement demand-loading. You should load pages only when they are referenced by the user process, as opposed to at process creation.
  • (harder) Implement paging. You should implement some page replacement algorithm and demonstrate your solution running under memory pressure.

Advanced Assignment Submission

Submission for the advanced assignment is similar to the basic assignment, except the advance component is given to a distinguished assignment name: asst3_adv

As for the basic assignment, you need to generate a .patches file. Make sure you and your partner have recorded all changes and pushed them to the repository in your group (/home/osprjXXX) directory. Then create a .patches file -- note the different name:

% cd ~/cs3231/asst3-src
% darcs send -o ~/asst3_adv.patches /home/cs3231/assigns/asst3/src

Submit your solution:

% cd ~
% give cs3231 asst3_adv asst3_adv.patches

You're now done.


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