References

  1. A. Aziz, F. Balarin, R.K. Brayton & A. L. Sangiovanni-Vincentelli (2000): Sequential synthesis using S1S. IEEE Transactions on Computer-Aided Design 19(10), pp. 1149–1162, doi:10.1109/43.875301.
  2. G. Barrett & S. Lafortune (1998): Bisimulation, the Supervisory Control Problem and Strong Model Matching for Finite State Machines. Discrete Event Dynamic Systems: Theory & Applications 8(4), pp. 377–429, doi:10.1023/A:1008301317459.
  3. Nikola Beneš, Benoît Delahaye, Uli Fahrenberg, Jan Křetínský & Axel Legay (2013): Hennessy-Milner Logic with Greatest Fixed Points as a Complete Behavioural Specification Theory. In: Pedro R. D'Argenio & Hernán Melgratti: CONCUR 2013 – Concurrency Theory. Springer Berlin Heidelberg, Berlin, Heidelberg, pp. 76–90, doi:10.1007/978-3-642-40184-8_7.
  4. A. Benveniste, B. Caillaud, A. Ferrari, L. Mangeruca, R. Passerone & C. Sofronis (2007): Multiple Viewpoint Contract-Based Specification and Design. In: Frank S. de Boer, Marcello M. Bonsangue, Susanne Graf & Willem-Paul de Roever: Formal Methods for Components and Objects. Springer Berlin Heidelberg, Berlin, Heidelberg, pp. 200–225, doi:10.1007/978-3-540-92188-2_9.
  5. A. Benveniste, B. Caillaud, D. Nickovic, R. Passerone, J.-B. Raclet, P. Reinkemeier, A. L. Sangiovanni-Vincentelli, W. Damm, T. A. Henzinger & K. G. Larsen (2018): Contracts for System Design. Foundations and Trends^89.5-.3em in Electronic Design Automation 12(2-3), pp. 124–400, doi:10.1561/1000000053.
  6. P. Bhaduri & S. Ramesh (2008): Interface synthesis and protocol conversion. Formal Asp. Comput. 20(2), pp. 205–224, doi:10.1007/s00165-007-0045-4.
  7. G. Bochmann (2013): Using logic to solve the submodule construction problem. Discrete Event Dynamic Systems 23(1), pp. 27–59, doi:10.1007/s10626-011-0127-6.
  8. Patricia Bouyer, Franck Cassez & François Laroussinie (2011): Timed Modal Logics for Real-Time Systems - Specification, Verification and Control. Journal of Logic, Language and Information 20(2), pp. 169–203, doi:10.1007/s10849-010-9127-4.
  9. J.R. Burch, D. Dill, E. Wolf & G. DeMicheli (1993): Modelling hierarchical combinational circuits. In: The Proceedings of the International Conference on Computer-Aided Design, pp. 612–617, doi:10.1109/ICCAD.1993.580149.
  10. Franck Cassez & François Laroussinie (2000): Model-Checking for Hybrid Systems by Quotienting and Constraints Solving. In: E. Allen Emerson & Aravinda Prasad Sistla: Computer Aided Verification. Springer Berlin Heidelberg, Berlin, Heidelberg, pp. 373–388, doi:10.1007/10722167_29.
  11. G. Castagnetti, M. Piccolo, T. Villa, N. Yevtushenko, R. K. Brayton & A. Mishchenko (2015): Automated Synthesis of Protocol Converters with BALM-II. In: D. Bianculli, R. Calinescu & B. Rumpe: Software Engineering and Formal Methods. SEFM 2015 Collocated Workshops: ATSE, HOFM, MoKMaSD, and VERY*SCART. York, UK, September 7-8, 2015, pp. 281–296, doi:10.1007/978-3-662-49224-6_23.
  12. E. Cerny & M. Marin (1977): An approach to unified methodology of combinational switching circuits. IEEE Transactions on Computers vol. C-26(8), pp. 745–756, doi:10.1109/TC.1977.1674912.
  13. W. Chen, J. Udding & T. Verhoeff (1989): Networks of communicating processes and their \voidb@x (de-)composition. In: J.L.A. van de Snepscheut: Mathematics of Program Construction, Lecture Notes in Computer Science 375. Springer Berlin Heidelberg, pp. 174–196, doi:10.1007/3-540-51305-1_10.
  14. L. De Alfaro (2003): Game Models for Open Systems. In: N. Dershowitz: Verification: Theory and Practice, Lecture Notes in Computer Science 2772. Springer Verlag, pp. 269–289, doi:10.1007/978-3-540-39910-0_12.
  15. L. De Alfaro & T. A. Henzinger (2001): Interface Automata. SIGSOFT Softw. Eng. Notes 26(5), pp. 109–120, doi:10.1145/503209.503226.
  16. M. D. Di Benedetto, A. Sangiovanni-Vincentelli & T. Villa (2001): Model Matching for Finite State Machines. IEEE Transactions on Automatic Control 46(11), pp. 1726–1743, doi:10.1109/9.964683.
  17. M. Fujita, Y. Matsunaga & M. Ciesielski (2001): Multi-Level Logic Optimization. In: R. Brayton, S. Hassoun & T. Sasao: Logic Synthesis and Verification. Kluwer, pp. 29–63, doi:10.1007/978-1-4615-0817-5_2.
  18. P. Green (1986): Protocol Conversion. IEEE Transactions on Communications 34(3), pp. 257–268, doi:10.1109/32.4655.
  19. E. Haghverdi & H. Ural (1999): Submodule construction from concurrent system specifications. Information and Software Technology 41(8), pp. 499–506, doi:10.1016/S0950-5849(99)00014-2.
  20. H. Hallal, R. Negulescu & A. Petrenko (2000): Design of divergence-free protocol converters using supervisory control techniques. In: 7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000 2, pp. 705–708, doi:10.1109/ICECS.2000.912975.
  21. S. Hassoun & T. Villa (2001): Optimization of Synchronous Circuits. In: R. Brayton, S. Hassoun & T. Sasao: Logic Synthesis and Verification. Kluwer, pp. 225–253, doi:10.1007/978-1-4615-0817-5_2.
  22. J.E. Hopcroft, R. Motwani & J.D. Ullman (2001): Introduction to Automata Theory, Languages, and Computation. Addison-Wesley Publishing Company, doi:10.1145/568438.568455.
  23. T. Kam, T. Villa, R. K. Brayton & A. L. Sangiovanni-Vincentelli (1997): Synthesis of FSMs: Functional Optimization. Kluwer Academic Publishers, Boston, doi:10.1007/978-1-4757-2622-0.
  24. J. Kim & M.M. Newborn (1972): The simplification of sequential machines with input restrictions. IRE Transactions on Electronic Computers, pp. 1440–1443, doi:10.1109/T-C.1972.223521.
  25. R. Kumar, S. Nelvagal & S.I. Marcus (1997): A discrete event systems approach for protocol conversion. Discrete Event Dynamic Systems: Theory & Applications 7(3), pp. 295–315, doi:10.1023/A:1008258331497.
  26. R.P. Kurshan, M. Merritt, A. Orda & S.R. Sachs (1999): Modelling asynchrony with a synchronous model. Formal Methods in System Design vol. 15(no. 3), pp. 175–199, doi:10.1007/3-540-60045-0_61.
  27. S. S. Lam (1988): Protocol Conversion. IEEE Trans. Softw. Eng. 14(3), pp. 353–362, doi:10.1109/32.4655.
  28. K.G. Larsen & L. Xinxin (1990): Equation solving using modal transition systems. In: Logic in Computer Science, 1990. LICS '90, Proceedings., Fifth Annual IEEE Symposium on e, pp. 108–117, doi:10.1109/LICS.1990.113738.
  29. N. Lynch & M. Tuttle (1989): An introduction to Input/Output automata. CWI-Quarterly 2(3), pp. 219–246, doi:10.1.1.83.7751.
  30. W.C. Mallon, J.T. Tijmen & T. Verhoeff (1999): Analysis and Applications of the XDI Model. In: International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 231–242, doi:10.1109/ASYNC.1999.761537.
  31. P. Merlin & G. v. Bochmann (1983): On the Construction of Submodule Specifications and Communication Protocols. ACM Transactions on Programming Languages and Systems 5(1), pp. 1–25, doi:10.1145/357195.357196.
  32. R. Negulescu (2000): Process spaces. In: C. Palamidessi: Proceedings of CONCUR 2000, 11th International Conference on Concurrency Theory, LNCS 1877. Springer-Verlag, pp. 199–213, doi:10.1007/3-540-44618-4_16.
  33. R. Passerone, L. De Alfaro, T. A. Henzinger & A. L. Sangiovanni-Vincentelli (2002): Convertibility verification and converter synthesis: two faces of the same coin. In: Lawrence T. Pileggi & Andreas Kuehlmann: ICCAD. ACM, pp. 132–139. Available at http://doi.acm.org/10.1145/774572.774592.
  34. R. Passerone, Í. Íncer Romeo & A. L. Sangiovanni-Vincentelli (2019): Coherent Extension, Composition, and Merging Operators in Contract Models for System Design. ACM Trans. Embed. Comput. Syst. 18(5s), doi:10.1145/3358216.
  35. R. Passerone, J. A. Rowson & A. L. Sangiovanni-Vincentelli (1998): Automatic Synthesis of Interfaces Between Incompatible Protocols. In: DAC, pp. 8–13. Available at http://doi.acm.org/10.1145/277044.277047.
  36. J.-B. Raclet, E. Badouel, A. Benveniste, B. Caillaud, A. Legay & R. Passerone (2011): A modal interface theory for component-based design. Fundamenta Informaticae 108(1-2), pp. 119–149, doi:10.3233/FI-2011-416.
  37. Í. Íncer Romeo, A. L. Sangiovanni-Vincentelli, C.-W. Lin & E. Kang (2018): Quotient for Assume-Guarantee Contracts. In: 16th ACM-IEEE International Conference on Formal Methods and Models for System Design, MEMOCODE ’18, pp. 67–77, doi:10.1109/MEMCOD.2018.8556872.
  38. E. Sentovich & D. Brand (2001): Flexibility in Logic. In: R. Brayton, S. Hassoun & T. Sasao: Logic Synthesis and Verification. Kluwer, pp. 65–88, doi:10.1007/978-1-4615-0817-5_2.
  39. T. Villa, A. Petrenko, N. Yevtushenko, A. Mishchenko & R. K. Brayton (2015): Component-Based Design by Solving Language Equations. Proceedings of the IEEE 103(11), pp. 2152–2167, doi:10.1109/JPROC.2015.2450937.
  40. T. Villa, N. Yevtushenko, R. K. Brayton, A. Mishchenko, A. Petrenko & A. L. Sangiovanni-Vincentelli (2012): The Unknown Component Problem: Theory and Applications. Springer, doi:10.1007/978-0-387-68759-9.
  41. S. Watanabe, K. Seto, Y. Ishikawa, S. Komatsu & M. Fujita (2007): Protocol Transducer Synthesis using Divide and Conquer approach. In: Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific, pp. 280–285, doi:10.1109/ASPDAC.2007.357999.
  42. N. Yevtushenko, T. Villa, R. K. Brayton, A. Mishchenko & A. L. Sangiovanni-Vincentelli (2004): Composition Operators in Language Equations. In: International Workshop on Logic and Synthesis, pp. 409–415.
Comments and questions to: eptcs@eptcs.org
For website issues: webmaster@eptcs.org