References

  1. L. Benini & G. De Micheli (2002): Networks on Chips: a new SoC paradigm. IEEE Computer 35(1), pp. 70–78, doi:10.1109/2.976921.
  2. Dominique Borrione, Amr Helmy, Laurence Pierre & Julien Schmaltz (2009): A formal approach to the verification of Networks on Chip. EURASIP Journal on Embedded Systems 2009, pp. 2:1–2:14, doi:10.1155/2009/548324.
  3. Satrajit Chatterjee & Michael Kishinevsky (2012): Automatic generation of inductive invariants from high-level microarchitectural models of communication fabrics. Formal Methods in System Design 40(2), pp. 147–169, doi:10.1007/s10703-011-0134-0.
  4. Satrajit Chatterjee, Michael Kishinevsky & Ümit Y. Ogras (2010): Quick formal modeling of communication fabrics to enable verification. In: Proceedings of the IEEE International High Level Design Validation and Test Workshop (HLDVT'10), pp. 42–49, doi:10.1109/HLDVT.2010.5496662.
  5. William James Dally & Brian Towles (2001): Route packets, not wires: on-chip interconnection networks. In: Design Automation Conference, 2001. Proceedings, pp. 684–689, doi:10.1109/DAC.2001.156225.
  6. Alexander Gotmanov, Satrajit Chatterjee & Michael Kishinevsky (2011): Verifying Deadlock-Freedom of Communication Fabrics. In: Verification, Model Checking, and Abstract Interpretation (VMCAI '11) 6538, pp. 214–231, doi:10.1007/978-3-642-18275-4_16.
  7. Daniel E. Holcomb, Alexander Gotmanov, Michael Kishinevsky & Sanjit A. Seshia (2012): Compositional performance verification of NoC designs. In: MEMOCODE. IEEE, pp. 1–10, doi:10.1109/MEMCOD.2012.6292294.
  8. Julien Schmaltz & Dominique Borrione (2008): A functional formalization of on chip communications. Formal Aspects of Computing 20(3), pp. 241–258, doi:10.1007/s00165-007-0049-0.
  9. Freek Verbeek (2013): Formal Verification of On-Chip Communication Fabrics. Radboud University Nijmegen.
  10. Freek Verbeek & Julien Schmaltz (2011): Hunting deadlocks efficiently in microarchitectural models of communication fabrics. In: Proceedings of the International Conference on Formal Methods in Computer-Aided Design, FMCAD '11. FMCAD Inc, Austin, TX, pp. 223–231. Available at http://dl.acm.org/citation.cfm?id=2157654.2157688.
  11. Freek Verbeek & Julien Schmaltz (2012): Easy Formal Specification and Validation of Unbounded Networks-on-Chips Architectures. ACM Transactions on Design Automation of Electronic Systems (TODAES) 17(1), doi:10.1145/2071356.2071357.

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