References

  1. Alexander Gotmanov, Satrajit Chatterjee & Michael Kishinevsky (2011): Verifying Deadlock-Freedom of Communication Fabrics. In: Ranjit Jhala & David A. Schmidt: VMCAI, Lecture Notes in Computer Science 6538. Springer, pp. 214–231. Available at http://dx.doi.org/10.1007/978-3-642-18275-4_16.
  2. W.C. Mallon & J.T. Udding (1998): Building finite automata from DI specifications. In: Proceedings of the Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems., pp. 184–193, doi:10.1109/ASYNC.1998.666504.
  3. F. Ouchet, K. Morin-Allory & L. Fesquet (2010): Delay Insensitivity Does Not Mean Slope Insensitivity!. In: 16th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'10), pp. 176–184, doi:10.1109/ASYNC.2010.27.
  4. A. Peeters, F. te Beest, M. de Wit & W. Mallon (2010): Click elements: An implementation style for data-driven compilation. In: Proceedings of the IEEE Symposium on Asynchronous Circuits and Systems (ASYNC'10), pp. 3–14, doi:10.1109/ASYNC.2010.11.
  5. Amir Pnueli (1977): The temporal logic of programs. In: 18th Annual Symposium on Foundations of Computer Science, pp. 46–57, doi:10.1109/SFCS.1977.32.
  6. Ivan Sutherland (2012): The tyranny of the clock. Communications of the ACM 55(10), pp. 35–36, doi:10.1145/2347736.2347749.
  7. F. Verbeek & J. Schmaltz (2011): Hunting deadlocks efficiently in microarchitectural models of communication fabrics. In: Proceedings of the International Conference on Formal Methods in Computer-Aided Design (FMCAD'11). IEEE, pp. 223–231.
  8. Freek Verbeek & Julien Schmaltz (2013): Formal Deadlock Verification for Click Circuits. In: 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'13).
  9. T. Verhoeff (1998): Analyzing specifications for delay-insensitive circuits. In: Proceedings of the Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 172–183, doi:10.1109/ASYNC.1998.666503.
  10. Chao Yan, F. Ouchet, L. Fesquet & K. Morin-Allory (2011): Formal Verification of C-element Circuits. In: 17th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'11), pp. 55–64, doi:10.1109/ASYNC.2011.14.
  11. Mohamed H. Zaki, Sofiène Tahar & Guy Bois (2008): Formal verification of analog and mixed signal designs: A survey. Microelectronics Journal 39(12), pp. 1395–1404, doi:10.1109/IDT.2009.5404084.

Comments and questions to: eptcs@eptcs.org
For website issues: webmaster@eptcs.org