Simulation under Arbitrary Temporal Logic Constraints

Julien Brunel
(ONERA DTIS and Université fédérale de Toulouse, France)
David Chemouil
(ONERA DTIS and Université fédérale de Toulouse, France)
Alcino Cunha
(INESC TEC and Universidade do Minho, Portugal)
Nuno Macedo
(INESC TEC and Universidade do Minho, Portugal)

Most model checkers provide a useful simulation mode, that allows users to explore the set of possible behaviours by interactively picking at each state which event to execute next. Traditionally this simulation mode cannot take into consideration additional temporal logic constraints, such as arbitrary fairness restrictions, substantially reducing its usability for debugging the modelled system behaviour. Similarly, when a specification is false, even if all its counter-examples combined also form a set of behaviours, most model checkers only present one of them to the user, providing little or no mechanism to explore alternatives. In this paper, we present a simple on-the-fly verification technique to allow the user to explore the behaviours that satisfy an arbitrary temporal logic specification, with an interactive process akin to simulation. This technique enables a unified interface for simulating the modelled system and exploring its counter-examples. The technique is formalised in the framework of state/event linear temporal logic and a proof of concept was implemented in an event-based variant of the Electrum framework.

In Rosemary Monahan, Virgile Prevosto and Jose Proença: Proceedings Fifth Workshop on Formal Integrated Development Environment (F-IDE 2019), Porto, Portugal, 7th October 2019, Electronic Proceedings in Theoretical Computer Science 310, pp. 63–69.
Published: 23rd December 2019.

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