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Aside: MIPS Branch Delay Slots

The real MIPS architecture is "pipelined" to improve efficiency
  • one instruction can start before the previous one finishes
For branching instructions (e.g. jal) ...
  • instruction following branch is executed before branch completes
To avoid potential problems use nop immediately after branch

A problem scenario, and its solution (branch delay slot): 

# Implementation of print(compute(42))
li   $a0, 42           li   $a0, 42
jal  compute           jal  compute
move $a0, $v0          nop
jal  print             move $a0,$v0
                       jal  print

Since SPIM is not pipelined, the nop is not required