Week 01 ------- A discussion was held to determine the interests of course participants. The following list of interesting topics was identified: o super-scalar processors; instruction-level parallelism o Itanium, PowerPC, Pentium architectures o VLIW o how to enhance performance through architectural improvements - how to measure improvement o architectural simulators o SIMD; multiprocessors; vector processors o buses; interconnection networks o memory; IRAM o specialized co-processors e.g. for graphics o embedded processors o varying the instruction-set architecture - tuning the ISA for particular application domains o hardware/software co-design o compiler <-> architecture support; hardware/software interaction o biocomputing; implanted hardware; neural networks; biologically inspired computing o pipelining & branch prediction o scalability Conclusion ---------- We will look at ILP and multiple issue processors (Hennessy & Patterson, 3ed, Ch. 3) and compilers support for static scheduling (Ch. 4) for the first 7 weeks or so. I then suggest we have a 3-4 week period during which Hardare/Software codesign, application specific instruction set processing, and design of specialized co-processors is studied. Finally, we will look at SIMD, multiprocessing, interconnection networks, and cluster computing for the last 3-4 weeks. Admin issues that need to be sorted out: ---------------------------------------- Students will present a seminar of between 1 and 1.5 hour duration. Students will keep a seminar log and actively participate in seminar discussions. Seminar presentation and participation will be marked. Students will also carry out a design project involving simulation of architectural enhancements. The idea is to work on current architectures and to enhance their performance for specific applications or emerging concepts in ICT. Students should gain experience with benchmarks & simulations in order to assess performance and evaluate improvements. There is also a desire that students should gain exposure to the literature in this area and get a taste of architectural research. Suggested marking scheme ------------------------ o Seminar presentation [20 marks] - preparation & quality of slides - presentation skill - ability to answer questions - ability to convey ideas . each dimension marked out of 5: . 1=poor, 2=marginal, 3=satisfactory, 4=good, 5=excellent o Seminar log [30 marks over 10 seminars] - attendance - be there [1 mark] - participation & contribution - ask questions & contribute solutions to problems [1 mark] - diary - keep log of readings, presentations, questions, and answers [1 mark] o Project [50 marks] - proposal - to be discussed & developed together with Oliver [10 marks] - design & implementation [15 marks] - results & conclusions [15 marks] - write-up - 10 - 20 page report expected [10 marks] Schedule -------- Week Date Seminars Refs 01 03/3 Discussion on scope Available texts 02 10/3 Oliver: Pipeline review; hazards Appendix A Ch. 3 03 17/3 Feri: Advanced pipelining App. A Oliver: Hazards; Scoreboarding Ch. 3 04 24/3 Oliver: Dynamic Scheduling & Branch Prediction Ch. 3 05 31/3 Oliver: Multiple Issue & Speculation Ch. 3 Yian: Vector Processors App. G 06 07/4 Boris: Ch 4.1 - 4.5 Ch. 4 Charles: Vector processing App. G 07 21/4 Oliver: Ch 4.6+ Ch. 4 Marco: Counterflow Pipeline Processor 08 28/4 Oliver Ch. 4 Emily: Power Aware Processor Design 09 05/5 Sri: HW/SW Codesign (?) Shannon: Reconfigurable Datapath 10 12/5 Newton: INSIDE Leo: Simultaneous Multithreading (Tullsen's paper) 11 19/5 Frank: DSP design Rampo: Flynn on Very High-Speed Computing Systems 12 26/5 Lih Wen: Processing in Memory/IRAM 13 02/6 Hiroshi: DNA computing 14 09/6