Models provided for 09s1

The following models have been tested with ISE 7.1i and are provided as is. Please respect any included copyright notices.

• Single cycle core 304919 Jul 31 12:26. The related block diagram can be found here.

The latter 3 models are provided as examples to be used in conjunction with the slides (4up) on VHDL testbenches and file access.

• Full adder testbench
• File I/O example
• File-based memory initialisation

Reference models

The following models are provided for reference in completing your assignments. The SPIM models are available from Sudhakar Yalamanchili's website. The Mano single cycle model was developed for Xilinx Foundation 2.1i at UNSW.

• Single cycle SPIM model
• Pipelined SPIM model
• Mano's single cycle CPU model